ZGAD125D12 — Chip (PIN)
Part Number

ZGAD125D12

ZGAD125D12

Product Summary

ZGAD125D12 is a dual-channel 12-bit 125Msps analog-to-digital converter (ADC), designed for high-frequency, wide dynamic range signal digitization, featuring excellent performance including 68dB Signal-to-Noise Ratio (SNR) and 85dB Spurious-Free Dynamic Range (SFDR) (SFDR).

Technical Specifications

• Sampling Rate 10Msps to 125Msps

• 1.8V Single Voltage Supply

• Output: DDR LVDS

• Input Range: 1.5V pp

• Signal-to-Noise Ratio (SNR): 68dB

• Spurious-Free Dynamic Range (SFDR): 85dB

• Full Power Bandwidth: 600MHz

• Power Dissipation at Full Rate: 400mW

• Dual-Channel Sampling

• Optional Clock Duty Cycle Stabilizer

• Power-Saving Low Power and Sleep Modes

• Configurable SPI Serial Port

• Package: QFN64

• Operating Temperature: -40°C to 85°C

Features & Benefits

ZGAD125D12 is a dual-channel 12-bit 125Msps analog-to-digital converter (ADC). designed for high-frequency, wide dynamic range signal digitization.The family features performance including 68dB Signal-to-Noise Ratio (SNR) and 85dB Spurious-Free Dynamic Range (SFDR) , making it perfect for demanding signal chain applications.600MHz input bandwidth allows the ADC to maintain excellent performance while sampling at high frequencies.The latency is only six clock cycles.Static specifications include ±0.6LSB Integral Non-Linearity (INL)(typical), ±0.25LSBDifferential Non-Linearity (DNL)(typical). The clock input can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS input.An optional clock duty-cycle stabilizer allows high performance at full-speed operation over a wide range of clock duty cycles.

Datasheets

PDFZGAD125D12.pdf
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PDFApplication Notes_ZG-0099.pdf
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PDFApplication Notes_ZG-0100.pdf
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PDFApplication Notes_ZG-0101.pdf
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